/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/**********************************************************************************************************************
 * File Name    : sysc_iobitmask.h
 * Version      : 1.00
 * Description  : IO bit mask file for sysc.
 *********************************************************************************************************************/
#ifndef SYSC_IOBITMASK_H
#define SYSC_IOBITMASK_H

#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWPU_Msk                    (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWPU_Pos                    (0UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWNS_Msk                    (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWNS_Pos                    (1UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWSEL_Msk                   (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWSEL_Pos                   (3UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARPU_Msk                    (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARPU_Pos                    (4UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARNS_Msk                    (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARNS_Pos                    (5UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARSEL_Msk                   (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARSEL_Pos                   (7UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWPU_Msk                    (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWPU_Pos                    (8UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWNS_Msk                    (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWNS_Pos                    (9UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWSEL_Msk                   (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWSEL_Pos                   (11UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARPU_Msk                    (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARPU_Pos                    (12UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARNS_Msk                    (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARNS_Pos                    (13UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARSEL_Msk                   (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARSEL_Pos                   (15UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWPU_Msk                    (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWPU_Pos                    (0UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWNS_Msk                    (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWNS_Pos                    (1UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWSEL_Msk                   (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWSEL_Pos                   (3UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARPU_Msk                    (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARPU_Pos                    (4UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARNS_Msk                    (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARNS_Pos                    (5UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARSEL_Msk                   (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARSEL_Pos                   (7UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWPU_Msk                    (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWPU_Pos                    (8UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWNS_Msk                    (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWNS_Pos                    (9UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWSEL_Msk                   (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWSEL_Pos                   (11UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARPU_Msk                    (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARPU_Pos                    (12UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARNS_Msk                    (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARNS_Pos                    (13UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARSEL_Msk                   (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARSEL_Pos                   (15UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWPU_Msk                  (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWPU_Pos                  (16UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWNS_Msk                  (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWNS_Pos                  (17UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWSEL_Msk                 (0x00080000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWSEL_Pos                 (19UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARPU_Msk                  (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARPU_Pos                  (20UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARNS_Msk                  (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARNS_Pos                  (21UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARSEL_Msk                 (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARSEL_Pos                 (23UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWPU_Msk                  (0x01000000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWPU_Pos                  (24UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWNS_Msk                  (0x02000000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWNS_Pos                  (25UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWSEL_Msk                 (0x08000000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWSEL_Pos                 (27UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARPU_Msk                  (0x10000000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARPU_Pos                  (28UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARNS_Msk                  (0x20000000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARNS_Pos                  (29UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARSEL_Msk                 (0x80000000UL)
#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARSEL_Pos                 (31UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWPU_Msk                   (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWPU_Pos                   (0UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWNS_Msk                   (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWNS_Pos                   (1UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWSEL_Msk                  (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWSEL_Pos                  (3UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARPU_Msk                   (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARPU_Pos                   (4UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARNS_Msk                   (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARNS_Pos                   (5UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARSEL_Msk                  (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARSEL_Pos                  (7UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWPU_Msk                   (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWPU_Pos                   (8UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWNS_Msk                   (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWNS_Pos                   (9UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWSEL_Msk                  (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWSEL_Pos                  (11UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARPU_Msk                   (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARPU_Pos                   (12UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARNS_Msk                   (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARNS_Pos                   (13UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARSEL_Msk                  (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARSEL_Pos                  (15UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWPU_Msk                   (0x00010000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWPU_Pos                   (16UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWNS_Msk                   (0x00020000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWNS_Pos                   (17UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWSEL_Msk                  (0x00080000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWSEL_Pos                  (19UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARPU_Msk                   (0x00100000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARPU_Pos                   (20UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARNS_Msk                   (0x00200000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARNS_Pos                   (21UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARSEL_Msk                  (0x00800000UL)
#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARSEL_Pos                  (23UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWPU_Msk                    (0x00000001UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWPU_Pos                    (0UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWNS_Msk                    (0x00000002UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWNS_Pos                    (1UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWSEL_Msk                   (0x00000008UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWSEL_Pos                   (3UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARPU_Msk                    (0x00000010UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARPU_Pos                    (4UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARNS_Msk                    (0x00000020UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARNS_Pos                    (5UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARSEL_Msk                   (0x00000080UL)
#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARSEL_Pos                   (7UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWPU_Msk                     (0x00000100UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWPU_Pos                     (8UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWNS_Msk                     (0x00000200UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWNS_Pos                     (9UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWSEL_Msk                    (0x00000800UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWSEL_Pos                    (11UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARPU_Msk                     (0x00001000UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARPU_Pos                     (12UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARNS_Msk                     (0x00002000UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARNS_Pos                     (13UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARSEL_Msk                    (0x00008000UL)
#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARSEL_Pos                    (15UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Msk                      (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Pos                      (2UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Msk                      (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Pos                      (4UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Msk                      (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Pos                      (6UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Msk                       (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Pos                       (0UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Msk                       (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Pos                       (2UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Msk                       (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Pos                       (4UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Msk                       (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Pos                       (6UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Msk                       (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Pos                       (10UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Msk                       (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Pos                       (12UL)
#define R_SYSC_SYS_SLVACCCTL3_CST_SL_Msk                        (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL3_CST_SL_Pos                        (0UL)
#define R_SYSC_SYS_SLVACCCTL3_CPG_SL_Msk                        (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL3_CPG_SL_Pos                        (2UL)
#define R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Msk                       (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Pos                       (4UL)
#define R_SYSC_SYS_SLVACCCTL3_SYC_SL_Msk                        (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL3_SYC_SL_Pos                        (6UL)
#define R_SYSC_SYS_SLVACCCTL3_GIC_SL_Msk                        (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL3_GIC_SL_Pos                        (8UL)
#define R_SYSC_SYS_SLVACCCTL3_IA55IM33_SL_Msk                   (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL3_IA55IM33_SL_Pos                   (10UL)
#define R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Msk                       (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Pos                       (12UL)
#define R_SYSC_SYS_SLVACCCTL3_MHU_SL_Msk                        (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL3_MHU_SL_Pos                        (14UL)
#define R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Msk                      (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Pos                      (2UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Msk                      (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Pos                      (4UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Msk                      (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Pos                      (6UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Msk                      (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Pos                      (8UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Msk                      (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Pos                      (10UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Msk                      (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Pos                      (12UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Msk                      (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Pos                      (14UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Msk                      (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Pos                      (16UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Msk                      (0x000C0000UL)
#define R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Pos                      (18UL)
#define R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Msk                       (0x00300000UL)
#define R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Pos                       (20UL)
#define R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Msk                       (0x00C00000UL)
#define R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Pos                       (22UL)
#define R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Msk                       (0x03000000UL)
#define R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Pos                       (24UL)
#define R_SYSC_SYS_SLVACCCTL4_RTC_SL_Msk                        (0x30000000UL)
#define R_SYSC_SYS_SLVACCCTL4_RTC_SL_Pos                        (28UL)
#define R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL5_POE3_SL_Msk                       (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL5_POE3_SL_Pos                       (2UL)
#define R_SYSC_SYS_SLVACCCTL5_GPT_SL_Msk                        (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL5_GPT_SL_Pos                        (4UL)
#define R_SYSC_SYS_SLVACCCTL5_POEG_SL_Msk                       (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL5_POEG_SL_Pos                       (6UL)
#define R_SYSC_SYS_SLVACCCTL5_DDR_SL_Msk                        (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL5_DDR_SL_Pos                        (8UL)
#define R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Msk                       (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Pos                       (10UL)
#define R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Msk                       (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Pos                       (12UL)
#define R_SYSC_SYS_SLVACCCTL6_USBT_SL_Msk                       (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL6_USBT_SL_Pos                       (0UL)
#define R_SYSC_SYS_SLVACCCTL6_USBT20_SL_Msk                     (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL6_USBT20_SL_Pos                     (2UL)
#define R_SYSC_SYS_SLVACCCTL6_USBT21_SL_Msk                     (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL6_USBT21_SL_Pos                     (4UL)
#define R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Msk                      (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Pos                      (6UL)
#define R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Msk                      (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Pos                      (8UL)
#define R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Msk                      (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Pos                      (10UL)
#define R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Msk                       (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Pos                       (12UL)
#define R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Msk                       (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Pos                       (14UL)
#define R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Msk                       (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Pos                       (16UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Msk                       (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Pos                       (0UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Msk                       (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Pos                       (2UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Msk                       (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Pos                       (4UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Msk                       (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Pos                       (6UL)
#define R_SYSC_SYS_SLVACCCTL7_I3C_SL_Msk                        (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL7_I3C_SL_Pos                        (8UL)
#define R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Msk                      (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Pos                      (10UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Msk                      (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Pos                      (12UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Msk                      (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Pos                      (14UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Msk                      (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Pos                      (16UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Msk                      (0x000C0000UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Pos                      (18UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Msk                      (0x00300000UL)
#define R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Pos                      (20UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Msk                      (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Pos                      (2UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Msk                      (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Pos                      (4UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Msk                      (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Pos                      (6UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Msk                      (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Pos                      (8UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Msk                      (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Pos                      (10UL)
#define R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Msk                       (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Pos                       (12UL)
#define R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Msk                       (0x0000C000UL)
#define R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Pos                       (14UL)
#define R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Msk                       (0x00030000UL)
#define R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Pos                       (16UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Msk                      (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Pos                      (2UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Msk                      (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Pos                      (4UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Msk                      (0x000000C0UL)
#define R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Pos                      (6UL)
#define R_SYSC_SYS_SLVACCCTL9_SRC_SL_Msk                        (0x00000300UL)
#define R_SYSC_SYS_SLVACCCTL9_SRC_SL_Pos                        (8UL)
#define R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Msk                      (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Pos                      (10UL)
#define R_SYSC_SYS_SLVACCCTL9_PDM_SL_Msk                        (0x00003000UL)
#define R_SYSC_SYS_SLVACCCTL9_PDM_SL_Pos                        (12UL)
#define R_SYSC_SYS_SLVACCCTL10_ADC_SL_Msk                       (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL10_ADC_SL_Pos                       (0UL)
#define R_SYSC_SYS_SLVACCCTL10_TSU_SL_Msk                       (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL10_TSU_SL_Pos                       (2UL)
#define R_SYSC_SYS_SLVACCCTL11_OTP_SL_Msk                       (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL11_OTP_SL_Pos                       (2UL)
#define R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Msk                     (0x00000C00UL)
#define R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Pos                     (10UL)
#define R_SYSC_SYS_SLVACCCTL12_CA55_SL_Msk                      (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL12_CA55_SL_Pos                      (0UL)
#define R_SYSC_SYS_SLVACCCTL12_CM33_SL_Msk                      (0x0000000CUL)
#define R_SYSC_SYS_SLVACCCTL12_CM33_SL_Pos                      (2UL)
#define R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Msk                   (0x00000030UL)
#define R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Pos                   (4UL)
#define R_SYSC_SYS_SLVACCCTL14_LSI_SL_Msk                       (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL14_LSI_SL_Pos                       (0UL)
#define R_SYSC_SYS_SLVACCCTL16_AOF_SL_Msk                       (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL16_AOF_SL_Pos                       (0UL)
#define R_SYSC_SYS_SLVACCCTL17_LP_SL_Msk                        (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL17_LP_SL_Pos                        (0UL)
#define R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Msk                     (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Pos                     (0UL)
#define R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Msk                    (0x00000003UL)
#define R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Pos                    (0UL)
#define R_SYSC_SYS_RAM0_ECC_VECCEN_Msk                          (0x00000001UL)
#define R_SYSC_SYS_RAM0_ECC_VECCEN_Pos                          (0UL)
#define R_SYSC_SYS_RAM0_EN_VCEN_Msk                             (0x00000001UL)
#define R_SYSC_SYS_RAM0_EN_VCEN_Pos                             (0UL)
#define R_SYSC_SYS_RAM0_EN_VLWEN_Msk                            (0x00000002UL)
#define R_SYSC_SYS_RAM0_EN_VLWEN_Pos                            (1UL)
#define R_SYSC_SYS_RAM1_ECC_VECCEN_Msk                          (0x00000001UL)
#define R_SYSC_SYS_RAM1_ECC_VECCEN_Pos                          (0UL)
#define R_SYSC_SYS_RAM1_EN_VCEN_Msk                             (0x00000001UL)
#define R_SYSC_SYS_RAM1_EN_VCEN_Pos                             (0UL)
#define R_SYSC_SYS_RAM1_EN_VLWEN_Msk                            (0x00000002UL)
#define R_SYSC_SYS_RAM1_EN_VLWEN_Pos                            (1UL)
#define R_SYSC_SYS_RAM2_ECC_VECCEN_Msk                          (0x00000001UL)
#define R_SYSC_SYS_RAM2_ECC_VECCEN_Pos                          (0UL)
#define R_SYSC_SYS_RAM2_EN_VCEN_Msk                             (0x00000001UL)
#define R_SYSC_SYS_RAM2_EN_VCEN_Pos                             (0UL)
#define R_SYSC_SYS_RAM2_EN_VLWEN_Msk                            (0x00000002UL)
#define R_SYSC_SYS_RAM2_EN_VLWEN_Pos                            (1UL)
#define R_SYSC_SYS_RAM3_ECC_VECCEN_Msk                          (0x00000001UL)
#define R_SYSC_SYS_RAM3_ECC_VECCEN_Pos                          (0UL)
#define R_SYSC_SYS_RAM3_EN_VCEN_Msk                             (0x00000001UL)
#define R_SYSC_SYS_RAM3_EN_VCEN_Pos                             (0UL)
#define R_SYSC_SYS_RAM3_EN_VLWEN_Msk                            (0x00000002UL)
#define R_SYSC_SYS_RAM3_EN_VLWEN_Pos                            (1UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Msk                        (0x00000001UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Pos                        (0UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Msk                    (0x00010000UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Pos                    (16UL)
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Msk                        (0x00000001UL)
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Pos                        (0UL)
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Msk                    (0x00010000UL)
#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Pos                    (16UL)
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Msk                        (0x00000001UL)
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Pos                        (0UL)
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Msk                    (0x00010000UL)
#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Pos                    (16UL)
#define R_SYSC_SYS_DDR_MCAR_CTRL_MCAR_CTRL_Msk                  (0x00010000UL)
#define R_SYSC_SYS_DDR_MCAR_CTRL_MCAR_CTRL_Pos                  (16UL)
#define R_SYSC_SYS_XSPI_MAP_STAADD_CS0_MAP_STAADD_CS0_Msk       (0xFFFFFFFFUL)
#define R_SYSC_SYS_XSPI_MAP_STAADD_CS0_MAP_STAADD_CS0_Pos       (0UL)
#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS0_MAP_ENDADD_CS0_Msk       (0xFFFFFFFFUL)
#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS0_MAP_ENDADD_CS0_Pos       (0UL)
#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS0_Msk       (0x00000001UL)
#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS0_Pos       (0UL)
#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS1_Msk       (0xFFFFFFFEUL)
#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS1_Pos       (1UL)
#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS0_Msk       (0x00000001UL)
#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS0_Pos       (0UL)
#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS1_Msk       (0xFFFFFFFEUL)
#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS1_Pos       (1UL)
#define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Msk                (0x01000000UL)
#define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Pos                (24UL)
#define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Msk                (0x01000000UL)
#define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Pos                (24UL)
#define R_SYSC_SYS_PCIE_CFG_ALLOW_ENTER_L1_Msk                  (0x00000100UL)
#define R_SYSC_SYS_PCIE_CFG_ALLOW_ENTER_L1_Pos                  (8UL)
#define R_SYSC_SYS_PCIE_MON_PMU_POWEROFF_Msk                    (0x00000001UL)
#define R_SYSC_SYS_PCIE_MON_PMU_POWEROFF_Pos                    (0UL)
#define R_SYSC_SYS_PCIE_MON_CLKL1PM_REQ_Msk                     (0x00000002UL)
#define R_SYSC_SYS_PCIE_MON_CLKL1PM_REQ_Pos                     (1UL)
#define R_SYSC_SYS_PCIE_MON_D_STATE_OUT_F0_Msk                  (0x00000030UL)
#define R_SYSC_SYS_PCIE_MON_D_STATE_OUT_F0_Pos                  (4UL)
#define R_SYSC_SYS_PCIE_ERR_MON_ERR_COR_DETECTED_F0_Msk         (0x00000001UL)
#define R_SYSC_SYS_PCIE_ERR_MON_ERR_COR_DETECTED_F0_Pos         (0UL)
#define R_SYSC_SYS_PCIE_ERR_MON_ERR_NONFATAL_DETECTED_F0_Msk    (0x00000002UL)
#define R_SYSC_SYS_PCIE_ERR_MON_ERR_NONFATAL_DETECTED_F0_Pos    (1UL)
#define R_SYSC_SYS_PCIE_ERR_MON_ERR_FATAL_DETECTED_F0_Msk       (0x00000004UL)
#define R_SYSC_SYS_PCIE_ERR_MON_ERR_FATAL_DETECTED_F0_Pos       (2UL)
#define R_SYSC_SYS_PCIE_PHY_MODE_RXTERMINATION_Msk              (0x00000001UL)
#define R_SYSC_SYS_PCIE_PHY_MODE_RXTERMINATION_Pos              (0UL)
#define R_SYSC_SYS_I2C0_CFG_af_bypass_Msk                       (0x00000001UL)
#define R_SYSC_SYS_I2C0_CFG_af_bypass_Pos                       (0UL)
#define R_SYSC_SYS_I2C1_CFG_af_bypass_Msk                       (0x00000001UL)
#define R_SYSC_SYS_I2C1_CFG_af_bypass_Pos                       (0UL)
#define R_SYSC_SYS_I2C2_CFG_af_bypass_Msk                       (0x00000001UL)
#define R_SYSC_SYS_I2C2_CFG_af_bypass_Pos                       (0UL)
#define R_SYSC_SYS_I2C3_CFG_af_bypass_Msk                       (0x00000001UL)
#define R_SYSC_SYS_I2C3_CFG_af_bypass_Pos                       (0UL)
#define R_SYSC_SYS_I3C_CFG_af_bypass_Msk                        (0x00000001UL)
#define R_SYSC_SYS_I3C_CFG_af_bypass_Pos                        (0UL)
#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Msk               (0xFFFFFFFCUL)
#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Pos               (2UL)
#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Msk               (0x000000FFUL)
#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Pos               (0UL)
#define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Msk                 (0x03FFFFFFUL)
#define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Pos                 (0UL)
#define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Msk                (0x03FFFFFFUL)
#define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Pos                (0UL)
#define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Msk                      (0xFFFFFF80UL)
#define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Pos                      (7UL)
#define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Msk                     (0xFFFFFF80UL)
#define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Pos                     (7UL)
#define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Msk                   (0x00000001UL)
#define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Pos                   (0UL)
#define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Msk                     (0x00000002UL)
#define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Pos                     (1UL)
#define R_SYSC_SYS_CM33FPU_CFG0_CONFIGSSYSTICK_Msk              (0x03FFFFFFUL)
#define R_SYSC_SYS_CM33FPU_CFG0_CONFIGSSYSTICK_Pos              (0UL)
#define R_SYSC_SYS_CM33FPU_CFG1_CONFIGNSSYSTICK_Msk             (0x03FFFFFFUL)
#define R_SYSC_SYS_CM33FPU_CFG1_CONFIGNSSYSTICK_Pos             (0UL)
#define R_SYSC_SYS_CM33FPU_CFG2_INITSVTOR_Msk                   (0xFFFFFFC0UL)
#define R_SYSC_SYS_CM33FPU_CFG2_INITSVTOR_Pos                   (6UL)
#define R_SYSC_SYS_CM33FPU_CFG3_INITNSVTOR_Msk                  (0xFFFFFFC0UL)
#define R_SYSC_SYS_CM33FPU_CFG3_INITNSVTOR_Pos                  (6UL)
#define R_SYSC_SYS_CM33FPU_LOCK_LOCKSVTAIRCR_Msk                (0x00000001UL)
#define R_SYSC_SYS_CM33FPU_LOCK_LOCKSVTAIRCR_Pos                (0UL)
#define R_SYSC_SYS_CM33FPU_LOCK_LOCKNSVTOR_Msk                  (0x00000002UL)
#define R_SYSC_SYS_CM33FPU_LOCK_LOCKNSVTOR_Pos                  (1UL)
#define R_SYSC_SYS_LSI_MODE_STAT_BOOTCPUSEL_Msk                 (0x00000001UL)
#define R_SYSC_SYS_LSI_MODE_STAT_BOOTCPUSEL_Pos                 (0UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Msk                    (0x00000070UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Pos                    (4UL)
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Msk                    (0x00000200UL)
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Pos                    (9UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Msk                    (0x00001000UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Pos                    (12UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BYPASS_Msk                  (0x00002000UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BYPASS_Pos                  (13UL)
#define R_SYSC_SYS_LSI_MODE_STAT_SEC_EN_Msk                     (0x00010000UL)
#define R_SYSC_SYS_LSI_MODE_STAT_SEC_EN_Pos                     (16UL)
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Msk                      (0x0000000FUL)
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Pos                      (0UL)
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Msk                      (0x000000F0UL)
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Pos                      (4UL)
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Msk                      (0x00000F00UL)
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Pos                      (8UL)
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Msk                      (0x0000F000UL)
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Pos                      (12UL)
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Msk                      (0x000F0000UL)
#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Pos                      (16UL)
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Msk                      (0x00F00000UL)
#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Pos                      (20UL)
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Msk                      (0x0F000000UL)
#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Pos                      (24UL)
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Msk                      (0xF0000000UL)
#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Pos                      (28UL)
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Msk                      (0x0000000FUL)
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Pos                      (0UL)
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Msk                      (0x000000F0UL)
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Pos                      (4UL)
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Msk                      (0x00000F00UL)
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Pos                      (8UL)
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Msk                      (0x0000F000UL)
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Pos                      (12UL)
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Msk                      (0x000F0000UL)
#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Pos                      (16UL)
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Msk                      (0x00F00000UL)
#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Pos                      (20UL)
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Msk                      (0x0F000000UL)
#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Pos                      (24UL)
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Msk                      (0xF0000000UL)
#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Pos                      (28UL)
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Msk                    (0x0000000FUL)
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Pos                    (0UL)
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Msk                    (0x000000F0UL)
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Pos                    (4UL)
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Msk                    (0x00000F00UL)
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Pos                    (8UL)
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Msk                    (0x0000F000UL)
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Pos                    (12UL)
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Msk                      (0x000F0000UL)
#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Pos                      (16UL)
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Msk                      (0x00F00000UL)
#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Pos                      (20UL)
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Msk                      (0x0F000000UL)
#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Pos                      (24UL)
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Msk                      (0xF0000000UL)
#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Pos                      (28UL)
#define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Msk                    (0x0000000FUL)
#define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Pos                    (0UL)
#define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Msk                    (0x000000F0UL)
#define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Pos                    (4UL)
#define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Msk                    (0x00000F00UL)
#define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Pos                    (8UL)
#define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Msk                    (0x0000F000UL)
#define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Pos                    (12UL)
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Msk                      (0x0000000FUL)
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Pos                      (0UL)
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Msk                      (0x000000F0UL)
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Pos                      (4UL)
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Msk                      (0x00000F00UL)
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Pos                      (8UL)
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Msk                      (0x0000F000UL)
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Pos                      (12UL)
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Msk                     (0x000F0000UL)
#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Pos                     (16UL)
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Msk                     (0x00F00000UL)
#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Pos                     (20UL)
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Msk                     (0x0F000000UL)
#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Pos                     (24UL)
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Msk                     (0xF0000000UL)
#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Pos                     (28UL)
#define R_SYSC_SYS_AOF9_OFS00_SXSDHI_2_Msk                      (0x0000000FUL)
#define R_SYSC_SYS_AOF9_OFS00_SXSDHI_2_Pos                      (0UL)
#define R_SYSC_SYS_AOF9_OFS01_SXDMAC_S_Msk                      (0x000000F0UL)
#define R_SYSC_SYS_AOF9_OFS01_SXDMAC_S_Pos                      (4UL)
#define R_SYSC_SYS_AOF9_OFS10_SXDMAC_S_Msk                      (0x00000F00UL)
#define R_SYSC_SYS_AOF9_OFS10_SXDMAC_S_Pos                      (8UL)
#define R_SYSC_SYS_AOF9_OFS11_SXDMAC_S_Msk                      (0x0000F000UL)
#define R_SYSC_SYS_AOF9_OFS11_SXDMAC_S_Pos                      (12UL)
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Msk                    (0x00000100UL)
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Pos                    (8UL)
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Msk                    (0x00001000UL)
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Pos                    (12UL)
#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_REQ_Msk                 (0x00002000UL)
#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_REQ_Pos                 (13UL)
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Msk                    (0x01000000UL)
#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Pos                    (24UL)
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Msk                    (0x10000000UL)
#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Pos                    (28UL)
#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_ACK_Msk                 (0x20000000UL)
#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_ACK_Pos                 (29UL)
#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Msk                     (0x00000001UL)
#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Pos                     (0UL)
#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Msk                     (0x00000002UL)
#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Pos                     (1UL)
#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Msk                     (0x00000004UL)
#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Pos                     (2UL)
#define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Msk                     (0x00000100UL)
#define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Pos                     (8UL)
#define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Msk                      (0x00000400UL)
#define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Pos                      (10UL)
#define R_SYSC_SYS_LP_CTL5_CM33FPUSLEEP_F_Msk                   (0x00000800UL)
#define R_SYSC_SYS_LP_CTL5_CM33FPUSLEEP_F_Pos                   (11UL)
#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Msk                     (0x00000002UL)
#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Pos                     (1UL)
#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Msk                     (0x00000004UL)
#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Pos                     (2UL)
#define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Msk                     (0x00000100UL)
#define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Pos                     (8UL)
#define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Msk                      (0x00000400UL)
#define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Pos                      (10UL)
#define R_SYSC_SYS_LP_CTL6_CM33FPUSLEEP_E_Msk                   (0x00000800UL)
#define R_SYSC_SYS_LP_CTL6_CM33FPUSLEEP_E_Pos                   (11UL)
#define R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk                        (0x00000001UL)
#define R_SYSC_SYS_LP_CTL7_IM33_MASK_Pos                        (0UL)
#define R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk                     (0x00000002UL)
#define R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Pos                     (1UL)
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Msk                    (0x00000001UL)
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Pos                    (0UL)
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Msk                    (0x00000010UL)
#define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Pos                    (4UL)
#define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Msk                  (0x00000200UL)
#define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Pos                  (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Msk              (0x00000002UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Pos              (1UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Msk              (0x00000004UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Pos              (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Msk               (0x00000100UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Pos               (8UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Msk              (0x00000200UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Pos              (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Msk             (0x00000400UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Pos             (10UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Msk            (0x00000800UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Pos            (11UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Msk                (0x00000002UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Pos                (1UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Msk                (0x00000004UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Pos                (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Msk                 (0x00000100UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Pos                 (8UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Msk                (0x00000200UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Pos                (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQAREQn_Msk              (0x00000400UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQAREQn_Pos              (10UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Msk              (0x00000800UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Pos              (11UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Msk        (0x00000001UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Pos        (0UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Msk             (0x00000002UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Pos             (1UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Msk             (0x00000004UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Pos             (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Msk              (0x00000100UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Pos              (8UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Msk             (0x00000200UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Pos             (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Msk            (0x00000400UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Pos            (10UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Msk           (0x00000800UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Pos           (11UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Msk                (0x00020000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Pos                (17UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Msk                (0x00040000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Pos                (18UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Msk                 (0x01000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Pos                 (24UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Msk                (0x02000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Pos                (25UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Msk               (0x04000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Pos               (26UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Msk              (0x08000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Pos              (27UL)
#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPMODE_Msk                 (0x00000001UL)
#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPMODE_Pos                 (0UL)
#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPDEEP_Msk                 (0x00000010UL)
#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPDEEP_Pos                 (4UL)
#define R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Msk               (0x00000200UL)
#define R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Pos               (9UL)
#define R_SYSC_SYS_PD_ISO_CTRL_PD_ISOVCC_ISOEN_Msk              (0x00000001UL)
#define R_SYSC_SYS_PD_ISO_CTRL_PD_ISOVCC_ISOEN_Pos              (0UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_EN_Msk            (0x00000001UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_EN_Pos            (0UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_Msk               (0x00000002UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_Pos               (1UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_EN_Msk            (0x00000010UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_EN_Pos            (4UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_Msk               (0x00000020UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_Pos               (5UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_EN_Msk            (0x00000100UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_EN_Pos            (8UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_Msk               (0x00000200UL)
#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_Pos               (9UL)
#define R_SYSC_ISO_IOBUF_SE18_CTRL_ISO_IOBUF_SE18_Msk           (0x00000001UL)
#define R_SYSC_ISO_IOBUF_SE18_CTRL_ISO_IOBUF_SE18_Pos           (0UL)
#define R_SYSC_SYS_USB_PWRRDY_PWRRDY_N_Msk                      (0x00000001UL)
#define R_SYSC_SYS_USB_PWRRDY_PWRRDY_N_Pos                      (0UL)
#define R_SYSC_SYS_PCIE_RST_RSM_B_PCIE_RST_RSM_B_Msk            (0x00000001UL)
#define R_SYSC_SYS_PCIE_RST_RSM_B_PCIE_RST_RSM_B_Pos            (0UL)
#define R_SYSC_SYS_GPREG_0_GPREG0_Msk                           (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_0_GPREG0_Pos                           (0UL)
#define R_SYSC_SYS_GPREG_1_GPREG1_Msk                           (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_1_GPREG1_Pos                           (0UL)
#define R_SYSC_SYS_GPREG_2_GPREG2_Msk                           (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_2_GPREG2_Pos                           (0UL)
#define R_SYSC_SYS_GPREG_3_GPREG3_Msk                           (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_3_GPREG3_Pos                           (0UL)
#define R_SYSC_SYS_IPCONT_SEL_SPI_OCTA_SEL_SPI_OCTA_Msk         (0x00000001UL)
#define R_SYSC_SYS_IPCONT_SEL_SPI_OCTA_SEL_SPI_OCTA_Pos         (0UL)
#define R_SYSC_SYS_IPCONT_IDAUZERONS_IDAUZERONS_Msk             (0x00000001UL)
#define R_SYSC_SYS_IPCONT_IDAUZERONS_IDAUZERONS_Pos             (0UL)
#define R_SYSC_SYS_IPCONT_IDAUZERONS_FPU_IDAUZERONS_FPU_Msk     (0x00000001UL)
#define R_SYSC_SYS_IPCONT_IDAUZERONS_FPU_IDAUZERONS_FPU_Pos     (0UL)

#endif
